The present invention relates to digital signal analyzing.
Characterizing the transient behavior of high-speed digital circuits, i.e. the transitions from a logical zero to a logical one and vice versa, has become increasingly important for designing as well as manufacturing such digital circuits. Timing problems can cause transmission errors, temporary or even permanent outage of an entire computing or communication system, and have to be avoided.
A standard characterization of digital circuits is the so-called Bit Error Ratio (BER) determination. Therefore, a received digital data signal is repetitively sampled at a defined sampling point. A sampling point is determined by a threshold value and by a relative time or time delay with respect to a clock signal associated to the data signal. The sampled values forming the sampled signal are each compared with corresponding values of an expected signal, and the ratio of erroneous bits to the total number of bits is determined.
Particularly, the BER depends on the quality of the received signal carrying the digital data. The signal quality significantly depends on characteristics of the transmission channel between the signal transmitter and the signal receiver. Such transmission channel, amongst others, might have low pass effects leading to data dependent distortions, e.g. to so-called inter-symbol interference -ISI- effects. Such effects often superpose with other distortions, e.g. random or periodic jitter that makes testing a signal transmitting device under test difficult. Especially, determining jitter properties directly from BER measurements of such received signal might lead to wrong results.
A further problem of testing a transmitting device is that in order to compensate for distortion effects of the communication channel, modern communication systems often use so-called pre- or de-emphasized signals. If these signals are measured directly at the output of the device, a deliberately distorted signal will be measured that might lead to wrong measurement results.
U.S. Pat. No. 5,726,991 A discloses an integral bit error rate test system.